The invention relates to fast recovery, i.e., fast "wakeup", biasing circuits for use in digital circuitry, and more particularly to analog-to-digital converters including such fast wakeup biasing circuitry, and also to methods for operating such analog-to-digital converters.
Some state-of-the-art successive-approximation analog-to-digital converters are provided with a "power down" operating mode, wherein a "power down" control signal is generated to turn off internal bias circuits after completion of an analog-to-digital conversion cycle (which, for a 12 bit analog-to-digital converter, requires approximately 15 or 16 clock cycles). This greatly reduces the power dissipation of the analog-to-digital converter during any time interval in which no analog-to-digital conversions are occurring.
Then, when an analog-to-digital conversion is desired, the "power down" control signal is removed. This turns the bias circuits back on, i,e., "wakes them up", so the desired analog-to-digital conversion cycle can begin.
A problem of the prior art is that the "wakeup" time required for the known bias circuits is very long. Since the long wakeup time must be included in the "effective" analog-to-digital conversion time, it greatly increases the effective analog-to-digital conversion time, and greatly reduces the maximum rate at which repetitive analog-to-digital conversion cycles can be performed. Since power is being dissipated during the long wakeup, the long effective conversion time also increases the total power dissipation of the analog-to-digital conversion system, because the percentage of time that the power down mode is in effect is decreased for a particular conversion frequency.
In FIG. 1, the portion indicated by numeral 10 is a conventional prior art bias control circuit, which includes P-channel MOSFETs P1 and P2, N-channel MOSFETs N1, N2 and N3, and resistor R1 connected as shown. During the analog-to-digital conversion mode, transistors P1, P2, N1, N2, and N3 all are on, and the bias control circuit 10 functions as a current mirror control circuit, producing a voltage V.sub.C on conductor 13 which is applied to the gate electrodes of P-channel current mirror output MOSFETs in the bias circuitry of the analog-to-digital converter.
During a power down cycle, N-channel MOSFET N3 is turned off, so no current flows through any of the components of bias control circuit 10. When the power down cycle is ended, all of the MOSFETs in bias control circuit 10 are turned on. The recovery of the voltage on conductor 13 to the desired bias voltage V.sub.C is very slow (typically 5 microseconds) resulting in the slow, long "wakeup" of the bias control circuit-mentioned above. Also, it is difficult to ensure that MOSFETs N1, N2, P1, and P2 actually will turn on. Therefore, in the prior art it is necessary to provide additional circuity to ensure that an initial current flows through MOSFETs P1, P2, N1, N2 and resistor R1 when MOSFET N3 is turned on to end the power down condition.
Known analog-to-digital converters having a power down feature are sometimes used in conjunction with a microcontroller or microprocessor to provide a data acquisition system in which low level analog signals are converted to digital signals under the control of the microcontroller; the resulting digital numbers are input to the microcontroller for further processing. The microcontroller is interrupted during each analog-to-digital conversion cycle. A typical microcontroller may operate with a clock signal having a frequency of several megahertz. The very slow wakeup or recovery time of the prior analog-to-digital converters necessitates "stretching" of a pulse of the fast microcontroller clock signal by as much as several microseconds or more to allow the recovery or "wakeup" of the bias circuit to occur before a new analog-to-digital conversion can occur. This results in long, inefficient interrupt/wait intervals during which the microcontroller is inactive.
There is a need for increasing the speed of digital circuits, especially analog-to-digital converters and the like which are sometimes operated in a powerdown mode. There also is a need to greatly reduce the overall power dissipation of such circuits, especially for battery powered applications.